Integration of 2D Materials for Application in Electronics

• Bárbara Canto (AMO GmbH)

Date

Friday 25 October 2024

Time

13:45 - 14:45 hour

Address

Gorlaeus Building
Einsteinweg 55
2333 CC Leiden

Room

BM.1.23

The semiconductor technology is an area that has been attracting attention due to the down scaling of field- effect transistors (FETs) with stronger performance over the last decades. In the last years the miniaturization of the devices reached the 10 nm node.1 The integration of 2D materials, most notably graphene, with conventional silicon CMOS circuits has emerged as a promising frontier. The 2D materials are one option to increase the performance of devices in the semiconductor silicon technology because these materials have good carrier transport properties while being ultimately thin. The compatibility of 2D materials with BEOL (Back-end-of-the-line) processing is a transformative development, paving the way for their seamless integration into existing silicon technology. This compatibility not only ensures a smoother integration process but also opens doors to enhanced circuit performance and novel functionalities. With graphene at the forefront, these materials possess remarkable electrical, thermal, and mechanical properties that can potentially revolutionize electronics, optoelectronics, and energy storage. As the technological landscape expands, forecasts point to substantial economic impacts, echoing the transformative effects of previous technological breakthroughs and they can be the key for the integration of complex devices on CMOS platforms.2,3 But, optimizing integration processes and 2D material-based devices is an ongoing topic in academia and for industrial applications.2,4 There is still a long way to go before graphene-based products will be available in the semiconductor or microelectronic industry. Although graphene device layers, specifically graphene field effect transistors (GFETs), have nowadays even been fabricated with competence on top of well-established CMOS or waveguide platforms5, there are still some issues in the fabrication process.6–13 For this optimization, the formation of high-quality interfaces is essential. Strategies such as interfacial layer engineering and functionalization techniques offer avenues to enhance the compatibility and performance of graphene-based devices within a silicon-centric environment. Precise doping control in graphene is essential for modulating its electronic properties to suit specific applications. Achieving controlled and uniform doping levels is critical for realizing desired device characteristics. Strategies such as chemical doping, electrostatic gating, and substitutional doping hold promise in enabling precise and tunable doping profiles, thereby expanding the versatility of graphene-based devices within silicon CMOS technology3. In this work we will show some of the fabrication processes that we are working on from small-scale devices using e-beam lithography to wafer-scale processing using photolithography on different substrates. And the issues related with the fabrication process like presence of resist residue after the lithography, dielectric compatibility, stability and growth, optimization of the metal contacts and the challenges in transfer 2D material to a substrate in wafer scale.

Acknowledgements

The authors acknowledge funding from the European Union’s Horizon 2020 research and innovation program under grant agreements 881603 (Graphene Flagship), 952792 (2D-EPL), 101099139 (FLATS), 863337 (WiPLASH), 101006963 (GreEnergy), 101016734 (MISEL), 971398 (ULTRAPHO), 101135168 (2D-ENGINE), 101135571 (AttoSwitch).

References

1. Akinwande, D. et al. Graphene and two-dimensional materials for silicon technology. Nature 573, 507–518 (2019).
2. Lemme, M. C., Akinwande, D., Huyghebaert, C. & Stampfer, C. 2D materials for future heterogeneous electronics. Nat Commun 13, 1392 (2022).
3. Wang, Z. Wafer-Scale Integration of 2D Materials for Application in High-Performance Electronics and Optoelectronics. in (Italy, 2023).
4. Neumaier, D., Pindl, S. & Lemme, M. C. Integrating graphene into semiconductor fabrication lines. Nat. Mater. 18, 525–529 (2019).
5. Soikkeli, M. et al. Wafer-Scale Graphene Field-Effect Transistor Biosensor Arrays with Monolithic CMOS Readout. ACS Appl. Electron. Mater. 5, 4925–4932 (2023).
6. Li, B. et al. Deep UV hardening of photoresist for shaping of graphene and lift-off fabrication of back-gated field effect biosensors by ion-milling and sputter deposition. Carbon 118, 43–49 (2017).
7. Yun, H. et al. Removal of photoresist residues and healing of defects on graphene using H2 and CH4 plasma. Applied Surface Science 463, 802–808 (2019).
8. Choi, A. et al. Residue-free photolithographic patterning of graphene. Chemical Engineering Journal 429, 132504 (2022).
9. Chen, S. et al. Tunable Adhesion for All-Dry Transfer of 2D Materials Enabled by the Freezing of Transfer Medium. Advanced Materials 2308950 (2024) doi: 10.1002/adma.202308950.
10. Cheng, Z. et al. Toward Intrinsic Graphene Surfaces: A Systematic Study on Thermal Annealing and Wet-Chemical Treatment of SiO2-Supported Graphene Devices. Nano Letters 11, 767–771 (2011).
11. Marinov, D. et al. Reactive plasma cleaning and restoration of transition metal dichalcogenide monolayers. npj 2D Materials and Applications 5, 17 (2021).
12. Lim, Y.-D. et al. Si-Compatible Cleaning Process for Graphene Using Low-Density Inductively Coupled Plasma. ACS Nano 6, 4410–4417 (2012).
13. Achra, S. et al. Enhancing interface doping in graphene-metal hybrid devices using H2 plasma clean. Applied Surface Science 538, 148046 (2021).